In electronic design automation (EDA), placement of objects (also referred to herein as circuits, circuit cells or cells) is generally understood to refer to the positioning of the circuit cells on a common substrate. The cells are subject to constraints specified by the user to limit their placement to certain geometric regions on the chip. For example, a constraint may dictate that a particular type of cell must be placed within a given geometric constraint region, and all remaining cells must be excluded from the constraint region.
Such constraint regions may include, for example, site rows (rows) and voltage areas (VAs). Rows define where cells of a particular site class may be placed. VAs define regions where cells of a particular voltage configuration may be placed. Other constraint regions are also used.
A current problem with both constraint regions, including rows and VAs is that they interact with other constraint regions of the same type. For example, when a VA's size is changed, adjacent VAs must be changed to ensure they do not overlap with the changed VA, thus rendering VA changes tedious and error prone.
Rows are slightly different but suffer from many of the same problems. Rows may overlap to enable a region containing cells of several different site classes. A single or a specific set of rows may occupy one region of the IC, while a different row may occupy an adjacent region of the IC. Like VAs, since a change in a row usually requires an adjustment in the adjacent rows, conventional techniques for modifying rows are tedious and error prone.